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MP1230A/31A/32A
CMOS Microprocessor Compatible Double-Buffered 12-Bit Digital-to-Analog Converter
FEATURES
* Superior Ruggedized 1230 Series: 2 KV ESD * Four Quadrant Multiplication * Stable, More Accurate Segmented DAC Approach - 0.2 ppm/C Linearity Tempco - 2 ppm/C Max Gain Error Tempco - Lowest Sensitivity to Amplifier Offset - Lowest Output Capacitance (COUT = 80pF) - Lower Glitch Energy * Monotonic over Temperature Range * * * * * Lower Data Bus Feedthrough @ CS = 1 VDD from +11 V to +16 V Latch-Up Free CMOS Technology 12-Bit Bus Version: MP1208/1209/1210 16-Bit Upgrade: MP7636A
GENERAL DESCRIPTION
The MP1230A series are superior pin for pin replacements for the 1230 series. The MP1230A series is manufactured using advanced thin film resistors on a double metal CMOS process which promotes significant improvements in reliability, latch-up free performance and ESD protection. The MP1230A series incorporates a unique decoding technique yielding lower glitch, higher speed and excellent accuracy over temperature and time. 12-bit linearity is achieved without trimming. Outstanding features include: - Stability: integral and differential linearity tempcos are rated at 0.2 ppm/C typical. Monotonicity is guaranteed over all temperature ranges. Scale factor tempco is a low 2 ppm/C maximum. - Low Output Capacitance: Due to smaller MOSFET switch geometries allowed by decoding, the output capacitance at IOUT1 and IOUT2 is a low 80pF / 40pF and 25pF / 65 pF. This less than half the competitive DAC 1230 series. Lower capacitance allows the MP1230A series to achieve settling times faster than 1 s for a 10 V step. Low Sensitivity to Output Amplifier Offset: The linearity error caused by amplifier offset is reduced by a factor of 2 in the MP1230A series over conventional R-2R DACs.
-
The MP1230A series uses a circuit which reduces transients in the supplies caused by DATA bus transitions at CS = 1.
SIMPLIFIED BLOCK DIAGRAM
VDD INPUT LATCH DB11-DB4 DB3-DB0 BYTE1/BYTE2 D
8 8
VREF RFB VREF IOUT1 IOUT2
DAC LATCH D Q
Q
8 12
LE
LE
D
4
Q
4
12
CS WR1
LE
XFER WR2 DGND
AGND
Rev. 2.00 1
MP1230A/31A/32A
ORDERING INFORMATION
Package Type
Plastic Dip Plastic Dip Plastic Dip SOIC SOIC SOIC
Temperature Range
-40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C -40 to +85C
Part No.
MP1230ABN MP1231ABN MP1232ABN MP1230ABS MP1231ABS MP1232ABS
INL (LSB)
+1/2 +1 +2 +1/2 +1 +2
DNL (LSB)
+3/4 +1 +2 +3/4 +1 +2
Gain Error (% FSR)
+0.4 +0.4 +0.4 +0.4 +0.4 +0.4
PIN CONFIGURATIONS
CS WR1 AGND DB7 DB6 DB5 DB4 VREF RFB DGND
1 2 3 4 5 6 7 8 9 10
See Packaging Section for Package Dimensions
20 19 18 17 16 15 14 13 12 11
VDD BYTE1/BYTE2 WR2 XFER DB8 (DB0, LSB) DB9 (DB1) DB10 (DB2) DB11 MSB (DB3) IOUT2 IOUT1
CS WR1 AGND DB7 DB6 DB5 DB4 VREF RFB DGND
1 2 3 4 5 6 7 8 9 10
20 19 18 17 16 15 14 13 12 11
VDD BYTE1/BYTE2 WR2 XFER DB8 (DB0, LSB) DB9 (DB1) DB10 (DB2) DB11 MSB (DB3) IOUT2 IOUT1
20 Pin PDIP (0.300") N20
20 Pin SOIC (Jedec, 0.300") S20
PIN OUT DEFINITIONS
PIN NO. 1 2 3 4 5 6 7 8 9 10 11 NAME CS WR1 AGND DB7 DB6 DB5 DB4 VREF RFB DGND IOUT1 DESCRIPTION Chip Select (Active Low) Write 1 (Active Low) Analog Ground Data Input Bit 7 Data Input Bit 6 Data Input Bit 5 Data Input Bit 4 Reference Input Voltage Feedback Resistor Digital Ground Current Output 1 20 16 17 18 19 DB8 (DB0) XFER WR2 BYTE1/ BYTE2 VDD 14 15 DB10 (DB2) DB9 (DB1) PIN NO. 12 13 NAME IOUT2 DB11 (DB3) DESCRIPTION Current Output 2 Data Input Bit 11 (MSB) Data Input Bit 3 Data Input Bit 10 Data Input Bit 2 Data Input Bit 9 Data Input Bit 1 Data Input Bit 8 Data Input Bit 0 (LSB) Transfer Control Signal (Active Low) Write 2 (Active Low) Byte Sequence Control Positive Power Supply
Rev. 2.00 2
MP1230A/31A/32A
ELECTRICAL CHARACTERISTICS (VDD = + 15 V, VREF = +10 V unless otherwise noted)
Parameter STATIC PERFORMANCE1 Resolution (All Grades) Integral Non-Linearity (Relative Accuracy) MP1230ABN/ATD/ABS MP1231ABN/ATD/ABS MP1232ABN/ATD/ABS Differential Non-Linearity MP1230ABN/ATD/ABS MP1231ABN/ATD/ABS MP1232ABN/ATD/ABS Gain Error Gain Temperature Coefficient2 Power Supply Rejection Ratio Output Leakage Current DYNAMIC PERFORMANCE2 Current Settling Time AC Feedthrough at IOUT1 REFERENCE INPUT Input Resistance DIGITAL INPUTS Logical "1" Voltage Logical "0" Voltage Input Leakage Current Input Capacitance2 ANALOG OUTPUTS2 Output Capacitance COUT1 COUT1 COUT2 COUT2 POWER SUPPLY Functional Voltage Range4 Supply Current VDD IDD +4.5 1.2 +16 2.0 +4.5 +16 2.0 V mA 80 40 65 25 100 60 85 45 100 60 85 45 pF pF pF pF DAC Inputs all 1's DAC Inputs all 0's DAC Inputs all 1's DAC Inputs all 0's VIH VIL ILKG 10 3.0 2.4 0.8 +1 3.0 0.8 +1 V V A pF RIN 5 10 20 5 20 k tS FT 1.0 1.0 sec mV p-p N INL +1/2 +1 +2 DNL +3/4 +1 +2 GE TCGE PSRR IOUT 0.5 5 1 +20 +10 +0.4 +3/4 +1 +2 +0.4 +2 +20 +200 % FSR ppm/C ppm/% nA RL=100, CL=13pF Full Scale Change to 1/2 LSB VREF=100kHz, 20Vp-p, sinewave Using Internal RFB Gain/Temperature |Gain/VDD| VDD = + 0.25V +1/2 +1 +2 LSB 12 12 Bits LSB Best Fit Straight Line Spec. (Max INL - Min INL) / 2 Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments FSR = Full Scale Range
VIN = 0, 5 V
All digital inputs = 0 V or all = 5 V
Rev. 2.00 3
MP1230A/31A/32A
ELECTRICAL CHARACTERISTICS (CONT'D)
Parameter SWITCHING CHARACTERISTICS2, 3 Chip Select to Write Set-Up Time Chip Select to Write Hold Time Data Valid to Write Set-Up Time Data Valid to Write Hold Time Write Pulse Width, tCS tCH tDS tDH tWR 200 10 100 90 100 100 0 50 70 50 ns ns ns ns ns Symbol Min 25C Typ Max Tmin to Tmax Min Max Units Test Conditions/Comments
NOTES:
1 2 3 4
Full Scale Range (FSR) is 10V. Guaranteed but not production tested. See timing diagram. Specified values guarantee functionality. Refer to other parameters for accuracy. Specifications are subject to change without notice
ABSOLUTE MAXIMUM RATINGS (TA = +25C unless otherwise noted)1, 2
VDD to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +17 V Digital Input Voltage to GND . . . . GND -0.5 to VDD +0.5 V IOUT1, IOUT2 to GND . . . . . . . . . . . . . . . . GND -0.5 to +6.5 V VREF to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V VRFB to GND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +25 V AGND to DGND . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . . +1 V (Functionality Guaranteed +0.5 V) Storage Temperature . . . . . . . . . . . . . . . . . -65C to +150C Lead Temperature (Soldering, 10 seconds) . . . . . . +300C Package Power Dissipation Rating to 75C CDIP, PDIP, SOIC . . . . . . . . . . . . . . . . . . . . . . . . . 900mW Derates above 75C . . . . . . . . . . . . . . . . . . . . . 12mW/C
NOTES: 1 Stresses above those listed under "Absolute Maximum Ratings" may cause permanent damage to the device. This is a stress rating only and functional operation at or above this specification is not implied. Exposure to maximum rating conditions for extended periods may affect device reliability. 2 Any input pin which can see a value outside the absolute maximum ratings should be protected by Schottky diode clamps (HP5082-2835) from input pin to the supplies. All inputs have protection diodes which will protect the device from short transients outside the supplies of less than 100mA for less than 100s. 3 GND refers to AGND and DGND.
Rev. 2.00 4
MP1230A/31A/32A
TIMING DIAGRAM
VIH VIL tWR 50% tDS 50% 50% tCS 50%
t CH
50%
CS, BYTE1/BYTE2
VIH WR VIL VIH DATA BITS VIL
tDH 50%
tS SETTLED TO +0.01%
IOUT1, IOUT2
DEFINITION OF CONTROL SIGNALS:
CS: WR1: Chip Select.(Active low) It will enable WR1. Write 1 (Active low) The WR1 is used to load the digital data bits (DB) into the input latch.
IOUT2: RFB:
DAC Current Output 2 Bus. IOUT2 is a complement of IOUT1. Feedback Resistor. This internal feedback resistor should always be used (not an external resistor) since it matches the resistors in the DAC and tracks these resistors over temperature. Reference Voltage Input. This input connects an external precision voltage source to the internal DAC. The VREF can be selected over the range of +25V to -25V or the analog signal for a 4-quadrant multiplying mode application. Power Supply Voltage. This is the power supply pin for the part. The VDD can be from +5 V DC to +15 V DC, however optimum voltage is +12 to +15 V DC.
BYTE1/BYTE2: Byte sequence control. The BYTE1/BYTE2 control pin is used to select both MSB and LSB input latches. WR2: XFER: Write 2 (Active low) It will enable XFER. Transfer control signal (Active low) This signal in combination with WR2 causes the 16-bit data which is available in the input latches to transfer to the DAC register
VREF:
VDD:
DB0 to DB11: Digital Inputs. DB0 is the least significant digital input (LSB) and DB11 is the most significant digital input (MSB). IOUT1: DAC Current Output 1 Bus. IOUT1 is a maximum for a digital code of all 1's in the DAC register, and is zero for all 0's in the DAC register.
AGND: Analog Ground Back gate of the DAC N-channel current steering switches. DGND: Digital Ground
Rev. 2.00 5
MP1230A/31A/32A
THEORY OF OPERATION
VDD VREF
DB11 (MSB) (DB3) DB10 (DB2) DB9 (DB1) DB8 (DB0) DB7 DB6 DB5 DB4
Q D Q D Q D D 8-Bit Q Input Q D D Latch Q Q D D LE Q D 4-Bit Q D Input Q D Latch Q D LE Q
Q D Q D Q D Q D Q D Q D D 12-Bit Q D DAC Q Register Q D Q D Q D D LE Q
MSB
RFB 12-Bit Multiplying D/A Converter
IOUT1
IOUT2 LSB
BYTE1/BYTE2 CS WR1 XFER WR2 DGND AGND
When LE = 1, Q Outputs Follow D Inputs When LE = 0, Q Outputs are Latched
Figure 1. Functional Diagram Digital Interface
Figure 1. shows the internal control logic that controls the writing of the input latches. It is easy to understand how the MP1230A/31A/32A works by understanding each basic operation.
Transferring Data to the DAC Latches
Writing to Input Latches
The condition BYTE1/BYTE2= high, CS = WR1 = 0 loads the data bus DB11-DB4 into both input latches. A second cycle with BYTE1/BYTE2 = low (Figure 2.) loads the pins DB11-DB8 (DB3-DB0) into the 4-bit input latch. Timing diagrams show the inputs CS and DB11-DB0 to be stable during the entire writing cycle. In reality all the above signals can change (Figure 2.) as long as they meet the timing conditions specified in the Electrical Characteristic Table.
Once one or all the input latches have been loaded, the condition XFER= WR2= low transfers the content of the input latches in the DAC latch. The outputs of the DAC latch change and the DAC current (IOUT) will reach a new stable value within the settling time tS (Figure 3.).
XFER WR2 DB11-0
or
or
CS BYTE1/BYTE2 DATA WR1
IOUT tS
Figure 3. Transfer Cycles from Input Latches to DAC Latches
Figure 2. Write Cycles to Input Latches
Rev. 2.00 6
MP1230A/31A/32A
PERFORMANCE CHARACTERISTICS
Graph 1. Relative Accuracy vs. Digital Code
APPLICATION NOTES Refer to Section 8 for Applications Information
Rev. 2.00 7
MP1230A/31A/32A
20 LEAD SMALL OUTLINE (300 MIL JEDEC SOIC) S20
D
20
11
E
H
10
h x 45 C Seating Plane e B A1 L A
INCHES SYMBOL A A1 B C D E e H h L MIN 0.097 0.0050 0.014 0.0091 0.500 0.292 MAX 0.104 0.0115 0.019 0.0125 0.510 0.299
MILLIMETERS MIN 2.464 0.127 0.356 0.231 12.70 7.42 MAX 2.642 0.292 0.483 0.318 12.95 7.59
0.050 BSC 0.400 0.010 0.016 0 0.410 0.016 0.035 8
1.27 BSC 10.16 0.254 0.406 0 10.41 0.406 0.889 8
Rev. 2.00 8
MP1230A/31A/32A
20 LEAD PLASTIC DUAL-IN-LINE (300 MIL PDIP) N20
S
20 1 Q1 D
11 10 E1 E A1
Seating Plane
A L B e B1
C
INCHES SYMBOL A A1 B B1 (1) C D E E1 e L MIN -- 0.015 0.014 0.038 0.008 0.945 0.295 0.220 MAX 0.200 -- 0.023 0.065 0.015 1.060 0.325 0.310
MILLIMETERS MIN -- 0.38 0.356 0.965 0.203 24.0 7.49 5.59 MAX 5.08 -- 0.584 1.65 0.381 26.92 8.26 7.87
0.100 BSC 0.115 0 0.055 0.040 (1) 0.150 15 0.070 0.080
2.54 BSC 2.92 0 1.40 1.02 3.81 15 1.78 2.03
Q1 S Note:
The minimum limit for dimensions B1 may be 0.023" (0.58 mm) for all four corner leads only.
Rev. 2.00 9
MP1230A/31A/32A Notes
Rev. 2.00 10
MP1230A/31A/32A Notes
Rev. 2.00 11
MP1230A/31A/32A
NOTICE EXAR Corporation reserves the right to make changes to the products contained in this publication in order to improve design, performance or reliability. EXAR Corporation assumes no responsibility for the use of any circuits described herein, conveys no license under any patent or other right, and makes no representation that the circuits are free of patent infringement. Charts and schedules contains here in are only for illustration purposes and may vary depending upon a user's specific application. While the information in this publication has been carefully checked; no responsibility, however, is assumed for inaccuracies. EXAR Corporation does not recommend the use of any of its products in life support applications where the failure or malfunction of the product can reasonably be expected to cause failure of the life support system or to significantly affect its safety or effectiveness. Products are not authorized for use in such applications unless EXAR Corporation receives, in writing, assurances to its satisfaction that: (a) the risk of injury or damage has been minimized; (b) the user assumes all such risks; (c) potential liability of EXAR Corporation is adequately protected under the circumstances. Copyright EXAR Corporation Datasheet April 1995 Reproduction, in part or whole, without the prior written consent of EXAR Corporation is prohibited.
Rev. 2.00 12

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